Be a significant part of the LTE PHY Silicon team, developing SSI’s next generation IOT chips.
Take part in all aspects of digital design – from architecture and specification, RTL design and verification
Development include complex signal processing blocks, requiring the application of solid insight in algorithmic and numerical considerations.
Close collaboration with the FW and DSP teams, Physical Design team and Production teams
Contribute to the development of a very complex state-of-the-art technological project
Development of a sophisticated low powered IOT solution
BSc with excellence in Electrical/Computer Engineering
At least 3 years of experience in ASIC design
Significant experience in development of signal processing blocks, preferably in wireless communication domain.
Background in wireless communication protocols, very low power design – advantage
Knowledge in Verilog, Specman and scripting languages – advantage
Knowledge in Matlab – advantage
Thinker, team player and motivated
Multi-disciplinary, self-learner, curious engineer